Engineers starting with the AM67A lose time before they lose anything else: the information exists, but it is not obvious which document holds it, several documents are published under a different chip's name, and two official pages answer the same question differently. This page is that map — which document answers which question, where the naming confusion comes from, and which source wins when official sources disagree. Every link below was opened and verified on 5 September 2026.
Which document answers which problem
| Problem | Document to open | Number |
|---|---|---|
| Pin, electrical limit, package, order code, variant difference | Datasheet | SPRSPA3B |
| Register, peripheral detail, block internals, memory map | Technical Reference Manual | SPRUJB3D |
| "The datasheet says this, but it doesn't work" | Silicon Errata | SPRZ575A |
| Whether a feature is actually supported in software | Software Build Sheet | Downloads tab of the SDK page |
| Linux, Yocto, device tree, drivers | Processor SDK Linux documentation | — |
| R5F, FreeRTOS, bare-metal, the MCU side | Processor SDK RTOS / MCU+ SDK (J722S) | — |
| Model compilation, TIDL, inference | Edge AI documentation and edgeai-tidl-tools |
— |
| Power estimation | Power Estimation Tool | datasheet §6.6 points to it |
| LPDDR4 routing and board design | Jacinto 7 LPDDR4 Board Design and Layout Guidelines | datasheet §8.2.1 cites it |
| Pin muxing and signal assignment | SysConfig | — |
| Board-level problems | The board's own documentation | — |
The naming problem: AM67A, AM67, J722S, TDA4VEN
This is why the page exists. The same silicon reaches you under at least five names.
| Name | What it is | Where you see it |
|---|---|---|
| AM67A | The production part with vision and deep-learning accelerators | Datasheet, product page, order code |
| AM67 | The same family member without the AI/vision accelerators | The same datasheet (it covers both) |
| J722S | The superset base part number for the family | TRM, errata, SDK, device tree, firmware filenames |
| TDA4VEN / TDA4AEN | Automotive siblings on the same silicon | Their own datasheets, a shared TRM title |
| Jacinto 7 | The architecture family name | Datasheet description, LPDDR4 guide title |
The root cause: each layer uses a different name.
| Layer | Name used | Evidence |
|---|---|---|
| Order code / product page | AM67A | AM67A94, AM67A74; ti.com/product/AM67A |
| Documents | J722S / TDA4VEN / TDA4AEN / AM67 | TRM and errata titles. The string "AM67A" never appears in the full text of the TRM; "AM67" and "J722S" appear on thousands of lines |
| Software | J722S | Device tree k3-j722s*.dtsi, compatible = "ti,j722s"; every firmware file is prefixed j722s-; Yocto machine j722s-evm; U-Boot j722s_evm_a53_defconfig; MCU+ SDK directory mcu_plus_sdk_j722s_* |
| SDK marketing | both AM67A and J722S | Two separate product pages at different versions (below) |
| Architecture | Jacinto 7 | Appears in the datasheet description, never in the TRM, lives on in the SDK hosting path (software-dl.ti.com/jacinto7/...) |
What this means in practice:
- Searching for "AM67A TRM" finds the document but not the name inside it. Opening the TRM and searching
AM67Areturns zero hits; you have to searchAM67orJ722S. - There is no
ti.com/product/J722Spage — it returns 404. J722S is a document and software name, not a name TI sells under. - There is no Yocto machine called
am67.meta-ticontains onlyj722s-evmandj722s-evm-k3r5, while the same directory holdsam68-skandam69-sk. So this inconsistency is specific to this part, not a family-wide convention. - In mainline Linux, every SoC-level device tree file carries the
k3-j722s*name. Files namedam67aare board-level (BeagleY-AI).k3-j722s.dtsilanded in v6.9;k3-am67a-beagley-ai.dtsin v6.12. - No RTOS or standalone MCU+ SDK is published under the AM67A name. The MCU side ships only inside the J722S SDK.
Seeing J722S in a document does not mean you are reading about the wrong chip. But the reverse does not hold either: because J722S is the superset, not every feature described in a J722S document exists on the AM67A. The datasheet warns about this explicitly and tells you to constrain software to the features of the target production device.
Silicon documents
Datasheet — SPRSPA3B
AM67x Processors, SPRSPA3B, March 2024, revised June 2026. https://www.ti.com/lit/ds/symlink/am67a.pdf
Answers: feature list, the variant comparison table (Table 4-1), speed grades, operating conditions, Power-On Hours, thermal resistance, eFuse programming conditions, power sequencing, pin list, package and order-code decoding.
Watch for:
- One document covers two parts (AM67 and AM67A). The feature list is the union of both; which feature belongs to which part is readable only from Table 4-1.
- This is why the
ti.com/product/AM67page can show "4 TOPS" — it comes from the shared feature block, and the AM67 part has no deep-learning accelerator. - Revision matters: revision B removed statements that revision A contained. An older copy on your disk may be carrying wrong information.
Technical Reference Manual — SPRUJB3D
J722S/TDA4VEN/TDA4AEN/AM67 Processor Silicon Revision 1.0 TRM, SPRUJB3D, March 2024, revised August 2026. https://www.ti.com/lit/zip/sprujb3
Answers: block internals (VPAC sub-modules, DMPAC engines, R5F subsystems), memory map, register definitions, which features are unsupported.
Watch for:
- TI does not offer this document as a PDF.
ti.com/lit/pdf/sprujb3does not work; only the ZIP path exists, and the archive is roughly 44 MB. Inside it you getSPRUJB3D.pdf(2400+ pages) plus a separate register-table spreadsheet. - To make search usable, download it and convert it to text locally; opening it in a browser and searching is not practical.
- The "Unsupported Features" headings are the most valuable and most skipped sections. A feature appearing in the datasheet does not mean the TRM supports it.
- Blocks may be named differently than in the datasheet — the datasheet uses the reference name
VPAC3Lwhere the TRM says only "VPAC".
Silicon Errata — SPRZ575A
J722S/TDA4VEN/TDA4AEN/AM67 Processor Silicon Revision 1.0 Errata, SPRZ575, Rev. A, April 2025. https://www.ti.com/lit/pdf/sprz575
Answers: known silicon behaviour that contradicts the datasheet, and the workarounds.
Watch for:
- The errata is older than the datasheet. Datasheet June 2026, errata April 2025. In the year between them the datasheet was revised twice and the errata was not.
- Before starting board design, confirm the current revision of both documents directly with TI.
- The errata's "Advisories by Modules" table is the fastest way to see which peripheral has a known problem.
Software documents — and the real trap here
This is the most practically useful section on the page.
TI publishes two separate SDK brands for the same silicon, and they do not move at the same pace. As of 5 September 2026:
| Page | SDK | Version | Release date |
|---|---|---|---|
| PROCESSOR-SDK-AM67A | Linux | 11.00.00.08 | 22 May 2025 |
| PROCESSOR-SDK-AM67A | Android | 11.00.01 | 23 February 2026 |
| PROCESSOR-SDK-J722S | Linux | 11.02.01.03 | 6 July 2026 |
| PROCESSOR-SDK-J722S | QNX | 11.02.01.03 | 1 July 2026 |
| PROCESSOR-SDK-J722S | RTOS | 11.02.01.03 | 6 July 2026 |
So the Linux SDK carrying the AM67A name is two minor versions and fourteen months behind the one carrying the J722S name. The AM67A page also has no RTOS SDK at all; if you intend to work on the R5F or C7x side you have to go to the J722S page.
Practical consequence: a team following only ti.com/tool/PROCESSOR-SDK-AM67A may be working on an old Linux SDK and never seeing the MCU side. If you are doing serious work on the AM67A, track both pages.
- Processor SDK AM67A: https://www.ti.com/tool/PROCESSOR-SDK-AM67A
- Processor SDK J722S: https://www.ti.com/tool/PROCESSOR-SDK-J722S
- AM67A Linux SDK docs: https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-am67a/latest/exports/docs/index.html
- J722S RTOS SDK docs: https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-j722s/latest/exports/docs/index.html
Software Build Sheet
The datasheet does not itself answer the question of which hardware feature is actually supported in software; in two separate places it redirects the reader to the Software Build Sheet. That document sits in the downloads tab of the SDK page.
This is the first document to open when validating an architecture plan: which core is open to application code, which peripheral has a driver, and which feature is in the "present in silicon, absent from the SDK" state are all read from here.
Edge AI and TIDL
edgeai-tidl-tools: https://github.com/TexasInstruments/edgeai-tidl-toolsedgeai-modelzoo: https://github.com/TexasInstruments/edgeai-modelzooedgeai-gst-apps: https://github.com/TexasInstruments/edgeai-gst-appsedgeai-tensorlab: https://github.com/TexasInstruments/edgeai-tensorlab- Edge AI Studio: https://www.ti.com/tool/EDGE-AI-STUDIO
Model compilation runs on a host machine and the resulting artifacts execute on the board. Which runtime version an artifact is compatible with depends on the match between these repositories' release tags and the SDK version — and if that match is not tracked, it is possible to get wrong results without any error message. The compile-side detail is covered separately in the TIDL model deployment page.
Full document inventory
Every document below was opened and verified on 5 September 2026. Revision letters and dates are the values valid that day.
Silicon and electrical
| Document | Number | URL |
|---|---|---|
| AM67x Processors datasheet | SPRSPA3 Rev. B | https://www.ti.com/lit/pdf/sprspa3 |
| Technical Reference Manual (ZIP) | SPRUJB3 Rev. D | https://www.ti.com/lit/zip/sprujb3 |
| Silicon Errata | SPRZ575 Rev. A | https://www.ti.com/lit/pdf/sprz575 |
| Power Estimation Tool User's Guide (ZIP) | SPRUJD0 Rev. A | https://www.ti.com/lit/zip/sprujd0 |
| BSDL model (ZIP) | SPRM854 | https://www.ti.com/lit/zip/sprm854 |
| IBIS model (ZIP) | SPRM855 | https://www.ti.com/lit/zip/sprm855 |
| Thermal model (ZIP) | SPRM856 | https://www.ti.com/lit/zip/sprm856 |
Board design
| Document | Number | URL |
|---|---|---|
| Jacinto 7 LPDDR4 Board Design and Layout Guidelines | SPRACN9 Rev. F | https://www.ti.com/lit/pdf/spracn9 |
| Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist | SPRAD91 Rev. B | https://www.ti.com/lit/pdf/sprad91 |
| Jacinto7 High-Speed Interface Design Guidelines | SPRACP4 Rev. A | https://www.ti.com/lit/pdf/spracp4 |
| Custom Board Design and Simulation Guidelines | SDAA087 Rev. A | https://www.ti.com/lit/pdf/sdaa087 |
| Automotive power design (with the TPS family) | SPRT775 | https://www.ti.com/lit/pdf/sprt775 |
| J722SXH01EVM evaluation board user's guide | SPRUJB5 | https://www.ti.com/lit/pdf/sprujb5 |
Security and production
| Document | Number | URL |
|---|---|---|
| Jacinto7 HS Device Development | SPRAD04 | https://www.ti.com/lit/pdf/sprad04 |
| Jacinto7 HS Device Customer Return Process | SPRADG2 | https://www.ti.com/lit/pdf/spradg2 |
| Security Enablers on Jacinto 7 Processors | SPRY339 | https://www.ti.com/lit/pdf/spry339 |
| TDA4 Flashing Techniques | SPRACY5 | https://www.ti.com/lit/pdf/spracy5 |
| OSPI Tuning Procedure | SPRACT2 | https://www.ti.com/lit/pdf/spract2 |
| TISCI Key Writer (key programming) | web | https://software-dl.ti.com/tisci/esd/latest/6_topic_user_guides/key_writer.html |
| Jacinto 7 Safety Product Overview | SPRAD57 | https://www.ti.com/lit/pdf/sprad57 |
Vision and Edge AI
| Document | Number | URL |
|---|---|---|
| AM6xA ISP Tuning Guide | SPRAD86 Rev. A | https://www.ti.com/lit/pdf/sprad86 |
| Driver/occupant monitoring with an RGB-IR camera | SPRADP7 Rev. A | https://www.ti.com/lit/pdf/spradp7 |
| Memory allocation for TIDL usage | SDAA177 | https://www.ti.com/lit/pdf/sdaa177 |
| Improving TIDL performance on C7x/MMA through memory | SDAA175 | https://www.ti.com/lit/pdf/sdaa175 |
| TIDLRunner: the "Bring Your Own Model" flow | SPRT832 | https://www.ti.com/lit/pdf/sprt832 |
| Designing an Efficient Edge AI System | SPRY344 Rev. A | https://www.ti.com/lit/pdf/spry344 |
| Debugging GPU driver problems | SPRADI3 | https://www.ti.com/lit/pdf/spradi3 |
| Improving timing with TSN Ethernet features | SPRADE9 | https://www.ti.com/lit/pdf/sprade9 |
Repositories
| Repository | What | URL |
|---|---|---|
edgeai-tidl-tools |
Model compilation | https://github.com/TexasInstruments/edgeai-tidl-tools |
edgeai-modelzoo |
Pre-built models | https://github.com/TexasInstruments/edgeai-modelzoo |
edgeai-gst-apps |
GStreamer reference applications | https://github.com/TexasInstruments/edgeai-gst-apps |
edgeai-gst-plugins |
TI GStreamer plugins | https://github.com/TexasInstruments/edgeai-gst-plugins |
edgeai-tensorlab |
Training and model preparation | https://github.com/TexasInstruments/edgeai-tensorlab |
ti-linux-firmware |
SYSFW / DM / IPC / HSM binaries | https://github.com/TexasInstruments/ti-linux-firmware |
meta-ti |
Yocto BSP layer | https://github.com/TexasInstruments/meta-ti |
When documents disagree
Working with the AM67A, official sources contradicting each other is not the exception — it is a regular occurrence. The known contradictions and which one governs:
| Contradiction | Where | Which governs |
|---|---|---|
The ti.com parametric table says "1 Arm Cortex-R5F"; the datasheet lists three R5F |
Product page ↔ datasheet | Datasheet and TRM |
The ti.com/product/AM67 page shows "4 TOPS"; the AM67 has no accelerator |
Product page ↔ Table 4-1 | Table 4-1 |
| The datasheet claims HS400 for eMMC; the errata reports it unsupported (i2478) | Datasheet ↔ errata | Errata |
| Temperature range: the nomenclature table and the package-options appendix give different values | Within the datasheet | Neither; ask TI |
| The datasheet treats C7x/MMA as closed to customer code; the MCU+ SDK lists C7x cores as open for development | Datasheet ↔ SDK | Unresolved; ask TI |
| C7x L2 SRAM size differs between datasheet and TRM | Datasheet ↔ TRM | Sibling datasheets support the datasheet value |
The general rule: datasheet for electrical and variant information, TRM for block internals, errata and Software Build Sheet for "does it actually work". The product page's parametric summary is a marketing summary and should not be used for technical decisions.
Related Spikedge pages
- TI AM67A SoC architecture — what the blocks are and how they connect
- AM67A vs AM62A processor selection — which part fits which system
- AM67A vision pipeline — where the latency goes between sensor and decision
- Linux and R5F real-time architecture — splitting work across the A53 and R5F cores
- T3 Gemstone O1 technical analysis — one AM67A board, read from its schematic
Upstream and community
- Mainline Linux device tree:
k3-j722s*files; board layersk3-am67a-* - U-Boot J722S EVM page: https://docs.u-boot.org/en/latest/board/ti/j722s_evm.html
meta-tiYocto layer: https://github.com/TexasInstruments/meta-ti- Linux remoteproc: https://docs.kernel.org/staging/remoteproc.html
- Linux rpmsg: https://docs.kernel.org/staging/rpmsg.html
- TI E2E forum: https://e2e.ti.com/support/processors-group/processors/f/processors-forum
