Interrupt Latency and the Deterministic Control Loop

TI-RTOS HWI direct dispatch · NVIC priority design · TI AM6442

TI AM6442 · TI-RTOS 7.x · Multi-Axis Servo Control

HWI direct dispatchInterrupt path

NVICPriority design

TicklessTimer

Priority ceilingShared resources

PlatformTI AM6442 · Dual Cortex-R5F

Problem classInterrupt latency and jitter turning into servo position drift

ApproachHWI direct dispatch + priority restructuring + tickless mode

MeasurementGPIO toggle output, external measurement equipment

01Problem

Problem: Where Interrupt Latency Grows

In a multi-axis servo control system the problem is not latency itself but latency that varies from cycle to cycle. Accumulated jitter turns into position error over sustained operation, and a missed deadline triggers a watchdog reset cycle. The goal is therefore not a lower average but a bounded, predictable worst case.

01Latency that varies cycle to cycle breaks the timing integrity of the control loop, and the accumulated error shows up as servo position drift
02High jitter makes repeatable position control impossible; a zero-defect threshold cannot be held in precision assembly
03Missed deadlines under sustained load trigger watchdog resets and force a restart
04When the RTOS tick interrupt shares an NVIC priority group with the control ISR, preemption delay stops being deterministic
05Logging and state updates inside the ISR spend the latency budget on work that does not belong on the critical path

02System Context

ProcessorTI AM6442. Dual Arm Cortex-R5F + Cortex-A53 cluster

RTOSFreeRTOS and TI-RTOS (SysBIOS kernel)

Active peripheralsPWM, QEP encoders, SPI-ADC

Control loopFixed time step, kHz range

Measurement methodGPIO toggle with external equipment. No software timestamps

Test conditionsSustained load, worst-case scenario

03Root Cause Analysis

01With NVIC priority grouping misconfigured, the RTOS tick interrupt shares a preemption level with the control ISR and preempts it
02Unnecessary stack copying on the scheduler context-switch path adds overhead to the critical path
03Without a priority ceiling protocol, priority inversion on a shared mutex produces non-deterministic wait times
04With timer coalescing enabled, unrelated interrupts are grouped together and produce latency variation
05Logging (UART DMA trigger) and shared-state updates inside the ISR move non-critical work onto the critical path
06Without dual-core resource planning both cores compete for interrupt handling and L1 cache thrashing appears

04What We Changed

Move from FreeRTOS to TI-RTOS (SysBIOS) HWI direct dispatch

→ Scheduler overhead leaves the critical ISR path entirely

Raise the control ISR to the highest NVIC priority level

→ Tick interrupt preemption risk disappears and preemption behaviour becomes predictable

Enable tickless mode and disable timer coalescing

→ Contention with the periodic tick interrupt goes away and a jitter source is removed

Move non-critical work out of the ISR into an SWI deferred handler

→ The critical path carries only the work that must happen at interrupt time

Redesign task-to-ISR communication with a zero-copy mailbox

→ Coordination between tasks no longer pays a copy cost

Pin critical tasks to one core and deferred work to the other

→ L1 cache thrashing is resolved and inter-core contention disappears

Apply the priority ceiling protocol to every shared mutex

→ Priority inversion is closed off, establishing ground for IEC 62443 compliance work

05Benchmark Results

06Why It Mattered

A deterministic control loop directly reduces operational and certification risk. What matters is not one good measurement but a worst case that stays bounded and repeatable under sustained load.

01The risk of missed deadlines and watchdog reset cycles is structurally reduced
02The accumulated timing error behind servo position drift is eliminated
03Work removed from the critical path frees CPU budget for runtime monitoring and fault logging
04A deterministic control loop scales to industrial robotics and precision assembly applications
05The priority ceiling protocol and RTOS choice establish technical ground for DO-178C and IEC 62443 compliance work

To evaluate your RTOS & Deterministic Control Systems needs on your own platform, schedule an embedded architecture audit or scope your platform class with the system requirements calculator.

Methodology Note

Latency is measured through a GPIO toggle output with external equipment; software timestamps carry measurement error
A large sample count is taken at every measurement point for statistical reliability and outlier analysis
Test conditions are defined under sustained load and worst case; an average is never reported on its own
Comparisons are made on identical hardware under identical test conditions, changing configuration only
This page describes a method. When a measurement is published, its setup and method sit next to the number

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This page describes a method, not a measurement report. Spikedge publishes only measurements taken on its own bench whose setup can be published; when a publishable measurement for this topic exists, it will be added here.