We don't list technologies, we demonstrate with metrics how we deliver results at hardware's theoretical limits. All data obtained on real hardware under repeatable conditions.
CASE 01 / boot-optimizationBSP & Yocto Optimization
Boot Time Architecture on Yocto Devices
NXP i.MX8M Plus · Yocto Scarthgap 5.0
Problem
On an industrial device, an image produced by a stock Yocto distribution brings the operator interface up only seconds after power-on. When the device is power-cycled several times a day, that time stops being a comfort issue and becomes time-to-operational-readiness.
Architectural Approach
U-Boot Falcon Mode takes the full U-Boot flow off the critical path and lets SPL load the kernel directly. Kernel compression moves from zlib to LZ4. The rootfs moves from ext4 to SquashFS with a tmpfs overlay. User space is rebuilt with musl libc and BusyBox.
Falcon Mode · LZ4 · SquashFSNXP i.MX8M Plus · Yocto
Falcon ModeBootloaderFull U-Boot flow off the critical path
LZ4Kernel compressionInstead of zlib
SquashFSRootfsRead-only + tmpfs overlay
Operational Impact
Boot time becomes an architectural decision. A read-only rootfs structurally reduces the risk of filesystem corruption on sudden power loss, and wiring boot-graph measurement into the build pipeline catches regressions before release.
CASE 02 / edge-ai-inferenceEdge AI & Computer Vision
Inference Pipeline Architecture on a Constrained Edge Device
NVIDIA Jetson Orin NX · TensorRT · JetPack
Problem
On a SWaP-C constrained platform, stock FP32 inference does not produce the throughput real-time detection and tracking need. Speed is not the only issue either: the power budget bounds mission time directly, which makes frames per watt the metric that matters.
Architectural Approach
INT8 quantization is applied, calibrated with a representative dataset. TensorRT engine serialization removes recompilation at startup. CUDA graphs collapse the per-frame kernel launch chain into a single graph. Suitable layers move to the DLA and pre-processing moves to the GPU.
INT8 · CUDA graphs · DLAJetson Orin NX · TensorRT
INT8QuantizationValidated on a calibration set
CUDA graphsKernel launchOne graph per frame
DLAWorkload splitCo-execution with the GPU
Operational Impact
More concurrent perception work fits into the same power budget. The INT8 calibration and validation flow is built as a reusable pipeline, and model updates take the same path.
CASE 03 / rtos-latencyRTOS & Deterministic Systems
Interrupt Latency and the Deterministic Control Loop
TI AM6442 · TI-RTOS
Problem
In a multi-axis motor control system the real problem is not latency itself but latency that varies from cycle to cycle. Accumulated jitter turns into position error over sustained operation, and a missed deadline triggers a watchdog reset cycle.
Architectural Approach
TI-RTOS HWI direct dispatch takes scheduler overhead off the critical ISR path. The control ISR moves to the highest NVIC priority level. Tickless mode is enabled and timer coalescing disabled. Non-critical work moves to an SWI deferred handler, and the priority ceiling protocol is applied to shared mutexes.
HWI dispatch · NVIC · ticklessTI AM6442 · TI-RTOS
HWI dispatchInterrupt pathScheduler leaves the critical path
The goal is a worst case that stays bounded and repeatable. Latency is measured through a GPIO toggle output with external equipment; software timestamps are not trusted.
Training a model to detect obstacles on the track requires images of rocks/branches/sacks/animals lying on the rails. But these "black-swan" events are rare, dangerous, and expensive to capture in reality, you cannot deliberately place an obstacle in front of a train. The result: a scarcity of positive samples and severe class imbalance.
Architectural Approach
In frames selected from forward-camera video, the rail corridor is found with YOLOv8-seg; transparent anomaly assets generated via SDXL + BiRefNet are placed on the rail with physically-correct scale referenced to the standard gauge (1.435 m), plus shadow and color harmonization. Labels are derived automatically from the post-transform visible alpha; at the video level a fixed track-id + KLT anchor keep it frame-consistent.
8 sınıf · 1.435 m gauge · otomatik etiketSDXL · BiRefNet · YOLOv8-seg
Critical obstacle scenarios, impossible to collect in the field, became available as synthetic, automatically labeled data. For autonomous railway safety (ODS) it targets the scarcity of positive samples and class imbalance in model training. (R&D, sim-to-real validation in progress.)
CASE 05 / webrtc-c2Industrial Video Streaming & Remote Monitoring
Low-Latency Industrial Video Transport Architecture
WebRTC · GStreamer · hardware-accelerated encode
Problem
In remote monitoring the operator decides on what is on screen, but in a classic RTSP chain what is on screen is a past scene. What matters is not the average delay but that the delay stays bounded and predictable.
Architectural Approach
The transport layer moves from RTSP/TCP to WebRTC P2P (UDP/SRTP). The GStreamer pipeline is rebuilt around hardware-accelerated H.264/H.265 encode. Buffering is retuned for live viewing. Video, sensor and telemetry travel on concurrent channels within one session.
WebRTC P2PTransportServer buffering and retransmits gone
HW encodeEncodingPredictable per-frame time
One sessionMulti-streamVideo + sensor + telemetry
Operational Impact
Operator decisions rest on a current image. A browser-native receiver removes install and version dependencies from the console, and adding a new sensor needs no architectural change.
CASE 06 / ethercat-motionIndustrial Protocols. Bench Measurement
Measuring Latency, Jitter and Packet Loss on an EtherCAT Bus
TI Sitara AM572x · TI-RTOS · Acontis EC-Master · TMS320F28388D
Problem
Getting axes on a machine to move together requires data to travel out and back in the same amount of time, every cycle. Standard Ethernet cannot guarantee that: a packet waits in a switch queue and on the OS scheduler, and its arrival time moves with load.
Architectural Approach
We built an EtherCAT bus on a TI Sitara AM572x IDK over the PRU-ICSS interface. TI-RTOS and Acontis EC-Master v3.2 on the master side, TMS320F28388D with Beckhoff SSC on the slave side. We then varied cycle frequency, payload size and slave count and measured how latency behaves.
A predictable per-cycle budget on standard Ethernet hardware. Raising the cycle from 1 kHz to 10 kHz costs no latency, and a second slave adds only 0.1 µs to the average.
* All performance data obtained in our own laboratory under repeatable conditions. Project-specific details are kept confidential under NDA. Methodology documentation available upon request.
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