Spikedge, microsecond-class deterministic embedded systems engineeringDeterminism
We take end-to-end technical ownership of systems where failure is not an option, from BSP to deterministic fieldbus architecture.
Watch the pipelineGeneration and labellingOur synthetic data pipeline · Railway obstacle detection (R&D)
01References
Organizations we work with
We don't share project details; this is who we work with, and how often.
- R01
Defense electronics
5+projects
- R02
Avionics and electronic systems
5+projects
- R03
FPGA, SoC and ASIC engineering
Collaboration
- R04
Technology training and workshop
Collaboration
02Silicon Ecosystem
We choose the silicon to fit the job
No vendor lock-in, select the optimum hardware for your project.
03Applications
What we build in the field
04Films
The problems we work on, on film
We build the scenes ourselves in Blender. Concept films illustrate a principle; a number appears on screen only when we measured it.
1:04ILLUSTRATION + BENCH DATAStraight to the GPU: zero-copy PCIe from TI Jacinto to Jetson Orin
1:00SYNTHETIC DATASynthetic data for railway obstacle detection: the rails are the ruler
1:01CONCEPT FILMReal time has a cost: when not to compute
1:36CONCEPT FILMThe object your vehicle cannot see: cooperative perception
05Reference Hardware
The silicon we work on
SoC, NPU, security module, fieldbus controller and real-time MCU, every block on a control board carries a different engineering responsibility. Touch a chip to see what we do at each layer.
Interactive, explore the silicon
06Engineering Capabilities
Real Systems, Published Setups
Every capability is exercised on real hardware; a published measurement comes with its setup.
07Industry Expertise
What each industry needs from embedded software
Industrial Automation
01Fault-tolerant, deterministic motor control and PLC integration, zero unplanned downtime
- Architecture that accounts for its failure modes from the start
- Deterministic fieldbus communication over EtherCAT
- Hard real-time motor control over EtherCAT
Agriculture & Autonomous
02Cloud-independent real-time anomaly detection on SWaP-C constrained edge devices
- Edge AI inference pipeline operating without cloud connectivity
- Real-time anomaly detection via multi-sensor fusion
- High-performance inference within tight SWaP-C power budgets
08Why Spikedge?
Measurable Engineering
Every number we publish has a setup and a method behind it.
Deterministic Interrupt Handling
We bound interrupt latency through NVIC priority design and direct interrupt dispatch, then verify the result with external measurement equipment.
Measurable Boot Architecture
U-Boot Falcon Mode, LZ4, SquashFS + tmpfs overlay. BSP architecture that cuts BOM cost.
Secure Boot + dm-verity
From hardware trust root to kernel isolation. Air-gapped repo, DevSecOps referenced to the ISO 27001 control set.
IEC 62443 · DO-178C requirements
Compliance is not an afterthought, it is a core architectural decision from the very first design session.
Algorithm → Silicon
Not fragmented components. We own the entire system, from BSP to Yocto distribution, for its full operational lifetime.
Engineering Proof Library
Latest technical publications, benchmark data and architecture profiles.
09How We Work
Deterministic Delivery Methodology
Discovery & Architecture
We start with NDA. Hardware constraints, latency requirements and regulatory framework are defined first.
BSP & Hardware Bring-up
Custom BSP from scratch, kernel optimization and secure boot chain for your specific hardware.
Integration & Test
We measure under repeatable conditions and deliver the setup and the method together with the report.
CVE Maintenance & OTA
Long-lifecycle industrial products need ongoing vulnerability management and fail-safe OTA update infrastructure.
The Deterministic Advantage
Not theoretical claims. Engineering grounded in measurement whose setup is published.
No Vendor Lock-In
NXP, NVIDIA, Hailo, TI, STM32, hardware-agnostic partnership. Resilience against supply chain pressure.
Regulatory Compliance from Day 1
IEC 62443, DO-178C, IEC 62304, built into architectural decisions, not bolted on at the end.
Measurement, Not Datasheet
The metrics we publish are taken on real hardware, and the setup they were measured on sits next to the number.
10-Year BSP Lifecycle
Industrial products live long. CVE maintenance, security patches and OTA infrastructure, for the full product lifecycle.
10Corporate Identity
An engineering team that measures and validates
Spikedge A.Ş. was founded in Bursa in 2026 and operates as an R&D center within Ulutek Technopark. The founding team brings 11+ years of field and design experience in embedded software and Edge AI to industrial automation, defense, and agricultural technology projects.
About Us- Founded
- 2026 · Bursa, Türkiye
- R&D Center
- Ulutek Technopark
- Founding Team Experience
- 11+ years
- Engagement Model
- NDA-compatible process
11Research Report
Reliable AI Integration on Constrained Edge Devices
Real-Time Reference Models for Industrial IoT and Precision Agriculture Systems
How can machine learning models scale despite hardware constraints in heavy industrial environments with intermittent connectivity and hard latency budgets? Explore our technical report on architectural approaches, analysing sensor fusion efficiency, RTOS task scheduling and power optimization strategies.
13Writing
The problems we work on
Straight to the GPU: Moving Frames over PCIe with DMA Instead of CPU Copies
When the CPU copies frames between two boards, the link sits idle. DMA, payload size, memory type and interrupts on PCIe Gen3 x4; 3.0–3.2 GB/s on our bench.
ReadReal Time Has a Cost: When Not to Compute and How to Choose N
Running the detector on every frame pays full price for what you already know. A cost model, an error budget and a method for choosing N, the detection interval.
ReadCooperative Perception: The Object Your Vehicle Cannot See
A larger model cannot see behind a container stack; a second viewpoint can. Roadside perception nodes, object-state messages, observation time and the safety chain.
ReadEtherCAT Explained: One Frame for Every Machine
In EtherCAT the master sends one frame per cycle; each device reads and writes its slot in hardware as it passes. FMMU, Working Counter, CAN and our bench numbers.
Read14Frequently Asked Questions
What technical buyers ask most often
- How do you work? Where does a project start?
- Most engagements start with an Architecture Audit: your current hardware/software architecture, bottlenecks, and measurement targets are clarified together. The audit deliverable includes a risk list, a recommended architecture, and a validation plan. Development then proceeds in sprints, each tied to a measurable technical outcome.
- How are NDA and intellectual property handled?
- We sign an NDA on every project. Ownership of code developed within the project scope is explicitly defined in the contract. Case studies on our website are published in anonymized form without disclosing client identity.
- How do you validate your performance figures?
- Latency and timing claims are validated with external instruments such as oscilloscopes and logic analyzers, not software timestamps, under defined load conditions and with repeatable test rigs. The measurement methodology is documented in the project report.
- Which hardware platforms do you work with?
- We have production experience on NVIDIA Jetson (Orin/Xavier), NXP i.MX 8/9, Hailo AI accelerators, Texas Instruments AM64x/Jacinto, and STM32/Cortex-M class platforms. For platforms outside this list, we can run an architectural fit assessment.
- Do you work remotely or on-site?
- We are based at Ulutek Technopark in Bursa, Türkiye. Development is largely remote; on-site work is planned for hardware bring-up, field measurement, and commissioning.
Strategic Technology Partnership
For Complex Engineering Challenges:
Strategic Technology Partnership
Whether you're designing HAL layers for a next-generation device or overcoming chronic performance and latency bottlenecks in an existing system, our engineering team is with you at every step. Let's evaluate your project's architectural feasibility, security regulations and technical risks together.